There are several techniques for making attenuators on GaAs, in particularly using monolithic microwave integrated circuit (MMIC) technology. The two main techniques use dual-gate FETs or single-gate FETs biased to have zero drain-source voltage (Vds=0).
PIN diode attenuators made using hybrid technology are not easily transposable to monolithic technology because of the difficulty of making PIN diodes on a GaAs substrate.
Attenuators based on single-gate FETs biased to have Vds=0 and as described in the literature do not provide very good performance with respect to insertion phase variation as a function of attenuation range.
However, tests have already been performed on dual-gate FET attenuators in attempts at achieving the desired objective. Most recent work relates to segmented dual-gate FET attenuators as described in the following two articles:
"A Microwave Phase and Gain Controller With Segmented Dual-Gate MESFETs in GaAs MMIC" by Y. C. Hwang, D. Temme, Y. K. Chen, and R. J. Naster (IEEE--Microwave and mm-Wave Monolithic Circuits Symposium--May 1984, pp. 1-5) describes a novel circuit constituted by a plurality of dual-gate FETs providing accurate gain control over a wide microwave band by virtue of an appropriate choice of gate width ratio: this accurate microwave gain control circuit has potential applications as an ultra wideband microwave attenuator or as an active microwave phase shifter.
"Segmented Dual-Gate MESFETs For Variable Gain and Power Amplifiers in GaAs MMIC" by K. H. Snow, J. J. Komiak, and D. A. Bates (IEEE--Trans. on MTT, vol. MTT-36, No. 12, December 1988, pp. 1976-1985) describes variable power and variable gain GaAs MMIC amplifier circuits using a dual-gate FET circuit.
These articles relate to digital attenuators constituted by a plurality of dual-gate FETs, each FET representing one bit. The insertion phase varies between 6.degree. and 10.degree. over an attenuation range of 20 dB depending on the frequency band. The principle used consists in minimizing insertion phase variation by individually optimizing the loads applied to the second gates of the dual-gate FETs constituting the various bits. The loads used are simple capacitances with different values from one bit to another. However, inlet and outlet reflection losses are not better than 6 dB because of the difficulty of matching the series of dual-gate FETs over the set of possible logic states.
The essential object of the invention is to provide such an attenuator while minimizing insertion phase variation as a function of attenuation.